
module riscv_inst_rom(
    input  clk,
    input  [31:0] inst_addr,
    output [31:0] inst_data
);

    wire [15:0] data_lo;
    wire [15:0] data_hi;

    inst_rom0 inst_rom_u0(
        .doa(data_lo),
        .addra(inst_addr[14:2]),
        .clka(clk)
    );

    inst_rom1 inst_rom_u1(
        .doa(data_hi),
        .addra(inst_addr[14:2]),
        .clka(clk)
    );

    assign inst_data[31:0] = {data_hi[15:0], data_lo[15:0]};

endmodule

